1. Field of the Invention
The present invention relates to a process for fabricating a semiconductor device. More specifically, it relates to a process for fabricating a multilayer interconnection structure of a semiconductor device.
2. Description of the Related Art
At present, a typical multilayer interconnection structure of a semiconductor device, such as for integrated circuits (IC), is fabricated in the following manner. For example, an aluminum alloy is deposited onto a selectively surface-oxidized silicon semiconductor bulk or substrate and patterned to form a lower wiring layer having patterns. Phospho-silicate glass (PSG) is then deposited onto the lower wiring layer and the exposed bulk by chemical vapor deposition (CVD) to form an insulating layer. After the necessary through-holes are opened in the insulating layer, an aluminum alloy is again deposited onto the insulating layer and in the through-holes and patterned to form an upper wiring layer having patterns electrically connected with the lower wiring layer through the through-holes.
In such a process, the lower wiring layer has abrupt steps at the shoulders of the patterns and narrow grooves between adjacent patterns in the same proximity. These steps and grooves cause insufficient coverage of the upper wiring layer on the insulating layer, since the insulating layer also has steps and grooves or cavities corresponding to those of the lower wiring layer. Such insufficient coverage of the upper wiring layer results in a decreased thickness and possible breakage of the upper wiring layer and causes migration and melting (resulting in breakage) of the upper wiring layer due to a concentration of the current.
To prevent such insufficient coverage of an upper wiring layer, a planarization process has been proposed in which, after forming the PSG insulating layer, a resin is coated onto the PSG insulating layer, thus planarizing the top surface of the insulating layer. In this process, however, an upper wiring layer is formed on the resin layer and, therefore, the material of the upper wiring layer, such as an aluminum alloy, is placed in contact with the resin layer just under the upper wiring layer and at the through-holes, thereby deteriorating the material of the upper wiring layer due to a chemical reaction between the upper wiring layer and the resin layer. Further, exposed portions of the resin layer are subjected to contact with chemicals or gases in later processes, causing cracks and etching etc. of the resin layer. These problems make the process unsuitable for practical use.
A process for planarizing a PSG layer on a polysilicon wiring layer is described by A. C. Adams and C. D. Capio, in the paper "Planarization of Phosphorus-Doped Silicon Dioxide" (J. Electrochem. Soc., Vol. 128, No. 2, February 1981). In this process, an organic material such as a photoresist is coated on a PSG layer to form a sacrificial layer having a relatively smooth top surface, and then etched using conditions in which the organic material and the PSG are etched at nearly the same rates, thereby maintaining the original profile of the coating material, leaving the PSG surface with only smooth, gentle steps. This process necessitates the use of a relatively thick PSG layer so as to at least fill the spaces between lower wiring layers. Such a thick PSG layer cannot be made without forming vacancies (spaces or gaps) therein. Formation of vacancies in the PSG layer may occur above the portions where two patterns of the lower wiring layer are spaced in the same proximity, and sometimes above near abrupt steps of the lower wiring layer. When etching for planarization is finished, vacancies may be opened at the top surface of the etched PSG layer, leaving open cavities and steps. Thus, insufficient coverage of an upper wiring layer when formed on the PSG layer having such cavities and steps again occurs. Further, the organic material such as a photoresist may enter the vacancies and remain there after the etching is completed, leaving organic material exposed on the top surface of the PSG layer. This exposed organic material may give rise to the same problems as mentioned previously. Thus, this planarization process is also insufficient for practical use.